sdivcc
Assembly Syntax
sdivcc regrs1, reg_or_imm, regrd
op3
011111
Operation
Signed division. Concatenates %y register with low 32 bits of regrs1, performs division and writes result as 32-bit number into regrd; %y register is undefined afterwards.
Comments
sets the condition codes
Example
sdivcc %r1, %r2, %r3
Example
sdivcc %r1, -2, %r1
Instruction format
Instruction format
