SPARC Architecture Online Reference Manual
FP
SPARC has a co-processor for executing floating point operations. It may have multiple additional and multiplication units that could function in parallel.
Floating point instructions work with floating point values. The register names from the floating point register file are %f0..%f31. These can be used as 32 32-bit registers or 16 64-bit or 8 128-bit registers.
When a value bigger than 32 bits has to be stored, more than one registers are used.
For double float values, 64 bits, a pair of even-odd registers are used. Only even-numbered registers may be specified and all memory locations must be 8-byte aligned.
For quads, 128-bit values, four registers are used.
fabss
faddd
faddq
fadds
fcmpd
fcmped
fcmpeq
fcmpes
fcmpq
fcmps
fdivd
fdivq
fdivs
fmovs
fmuld
fmulq
fmuls
fnegs
fsmuld
fsmulq
fsqrtd
fsqrtq
fsqrts
fsubd
fsubq
fsubs
ld
ldd
st
std